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irmck171 1 www.irf.com ? 20 14 international rectifi er submit datasheet feedback may 28, 2014 high performance sensorless motor control ic description irmck171 is a high performance one time programmable rom based motion control ic designed and optimized for appliance control which contains two computation engines integrated into one monolit hic chip. one is the flexible motion control engine (mce tm ) for sensorless control of permanent magnet motors or induction motors; the other is an 8 - bit high - speed microcontroller (8051). the user can program a motion control algorithm by connecting these control elements using a graphic compiler. key components of the complex sensorless control algorithms, such as the angle estimator, are provided as complete pre - defined control blocks. a unique analog/digital circuit and algorithm fully support s single sh unt or leg shunt current reconstruction. irmck171 comes in a 48 pin qf p package . features ? mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? built - in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits ? supports induction machine and both interior and surface permanent magnet motor sensorless control ? loss minimization space vector pwm ? two - channel analog output (pwm) ? embedded 8 - bit high spee d microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for e mulation/debugger ? serial communication interface (uart) ? i2c/spi serial interface ? internal 32kbyte otp rom ? 3.3v single supply product summary maximum clock input ( fcrystal) 60 mhz maximum internal clock (sysclk) 128mhz maximum 8051 clock (8051clk) 32mhz mce tm computation data range 16 bit signed 8051/mce data ram 2kb mce program ram 12kb pwm carrier frequency 20 bits/ sysclk a/d input channels 7 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6 kbps number of digital i/o (max) 10 package (lead free) qfp48 maximum 3.3v operating current 60ma base part number package type standard pack orderable part number form quantity irmck171 qfp tray 2500 irmck171 ty tape and reel 2000 irmck171 tr
irmck171 2 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 table of content s 1 overview ............................................................................................................................... 5 2 pinout .................................................................................................................................... 6 3 irmck171 block diagram and main functions .................................................................... 7 4 application connection and pin function ............................................................................... 9 4.1 8051 peripheral inte rface group ................................................................................. 10 4.2 motion peripheral interface group .............................................................................. 11 4.3 analog interface group ............................................................................................... 11 4.4 power interface group ................................................................................................ 11 4.5 test interface group ................................................................................................... 11 5 dc characteristics .............................................................................................................. 13 5.1 absolute maximum ratings ......................................................................................... 13 5.2 system clock frequency and power consumption .................................................... 13 5.3 d igital i/o dc characteristics ...................................................................................... 14 5.4 analog i/o (ifb+,ifb - ,ifbo, ain5+,ain5- ,ain5o) dc characteristics ...................... 15 5.5 under voltage lock out dc characteristics .................................................................. 16 5.6 itrip comparator dc characteristics ............................................................................. 16 5.7 cmext and aref characteristics ............................................................................. 16 6 ac characteristics .............................................................................................................. 17 6.1 digital pll ac characteristics .................................................................................... 17 6.2 analog to digital c onverter ac characteristics ........................................................... 18 6.3 op amp ac characteristics ......................................................................................... 19 6.4 sync to svpwm and a/d conversion ac timing ..................................................... 20 6.5 gatekill to svpwm ac timing ............................................................................... 21 6.6 itrip ac timing ............................................................................................................. 21 6.7 interrupt ac tim ing ..................................................................................................... 22 6.8 i 2 c ac timing .............................................................................................................. 22 6.9 spi ac timing ............................................................................................................. 23 6.10 uart ac ti ming ......................................................................................................... 25 6.11 capture input ac timing ........................................................................................ 26 6.12 otp programming timing ........................................................................................... 27 6.13 jtag ac timing ......................................................................................................... 28 7 i/o structure ........................................................................................................................ 29 8 pin list ................................................................................................................................ 32 9 package dimensions .......................................................................................................... 34 10 part marking information ..................................................................................................... 35 11 qualification information ..................................................................................................... 35
irmck171 3 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 list of tables table 1 absolute maximum ratings ........................................................................................... 13 table 2 system clock frequency ............................................................................................... 13 table 3 digital i/o dc characteristics ........................................................................................ 14 table 5 analog i/o dc characteristics ....................................................................................... 15 table 6 uvcc dc characteristics ............................................................................................... 16 table 7 itrip dc characteristics .................................................................................................. 16 table 8 cmext and aref dc characteristics .......................................................................... 16 table 9 pll ac characteristics .................................................................................................. 17 table 10 a/d converter ac characteristics ............................................................................... 18 table 11 current sensing op amp ac characteristics .............................................................. 19 table 12 sync ac characteristics ............................................................................................ 20 table 13 gatekill to svpwm ac timing ................................................................................ 21 table 14 itrip ac timing ............................................................................................................. 21 table 15 interrupt ac timing ...................................................................................................... 22 table 16 i 2 c ac timing .............................................................................................................. 22 table 17 spi write ac timing .................................................................................................... 23 table 18 spi read ac timing .................................................................................................... 24 table 19 uar t ac timing ......................................................................................................... 25 table 20 capture ac timing .................................................................................................. 26 table 21 otp programming timing ........................................................................................... 27 table 22 jtag ac timing .......................................................................................................... 28 table 23 pin list ......................................................................................................................... 33
irmck171 4 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 list of figures figure 1 typical ap plication block diagram using irmck171 ................................ ................................ ........ 5 figure 2 pinout of irmck171 ................................ ................................ ................................ ........................... 6 figure 3 crystal circuit example ................................ ................................ ................................ ...................... 17 figure 4 voltage droop and s/h hold time ................................ ................................ ................................ ...... 18 figure 5 a capacitor of 47pf is recommended at the output pin of all op amps. ................................ ........... 19 figure 6 sync timing ................................ ................................ ................................ ................................ ..... 20 figure 7 gatekill timing ................................ ................................ ................................ ................................ ... 21 figure 8 itrip timing ................................ ................................ ................................ ................................ ...... 21 figure 9 interrupt timing ................................ ................................ ................................ ................................ .. 22 figure 10 i 2 c timing ................................ ................................ ................................ ................................ ....... 22 figure 11 spi write ti ming ................................ ................................ ................................ ............................... 23 figure 12 spi read timing ................................ ................................ ................................ ............................... 24 figure 13 uart timing ................................ ................................ ................................ ................................ .... 25 fi gure 14 capture timing ................................ ................................ ................................ ............................ 26 figure 15 otp programming timing ................................ ................................ ................................ ................ 27 figure 16 jtag timing ................................ ................................ ................................ ................................ .... 28 figure 17 pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh output ................................ .................... 29 figure 18 all digital i/o except motor pwm output ................................ ................................ ......................... 29 figure 19 reset, gatekill i/o ................................ ................................ ................................ ................... 30 figure 20 analog input ................................ ................................ ................................ ................................ .... 30 figure 21 analog operational amplifier output and aref i/o struc ture ................................ ....................... 3 0 figure 22 vpp programming pin i/o structure ................................ ................................ ................................ 31 figure 23 vss and avss pin structure ................................ ................................ ................................ .......... 31 figure 24 vdd1 and vddcap pin structure ................................ ................................ ................................ .. 31 figure 25 xtal0/xtal1 pins structure ................................ ................................ ................................ .......... 31
irmck171 5 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 1 overview irmck171 is a new generation inter national rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. unlike a traditional microcontroller or dsp, the irmck171 provides a built - in closed loop sensorle ss control algorithm using the unique f lexible motion control engine ( mce tm ) for permanent magnet motors as well as induction motors . the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmck171 also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor int erface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented i n the 8051 high - speed 8 - bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using the irmck171. irm ck171 contains 32k bytes of otp program rom, the irmcf171 contains 64k bytes of flash ram and intended for development purposes only while the irmck171 is intended for volume production. both the development and rom versions come in a 48- pin qfp package wi th identical pin configuration to facilitate pc board layout and transition to mass production. irmck 171 power supply irs2336d pm motor ipm or spm or im motor passive emi fillter digital i/o analog input host communication (rs232c) appliance pm motor drive 3.3v gate signal 15v eeprom 6 2 8 galvanic isolation optional figure 1 typical application block diagram using irmck171
irmck171 6 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 2 pinout pin out shown is based on qfp48 p in package. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 16 3 12 4 11 5 6 7 8 9 10 2 1 xtal0 xtal1 p1.1/rxd p1.2/txd vdd1 vss vddcap p1.3/sync/sck p1.4/cap p3.2/int0 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 vss vddcap avss aref p2.7/aopwm1 pwmuh pwmvh pwmwh pwmul pwmvl pwmwl gatekill ifbo ifb+ ifb- reset vpp/p1.5 tck tdi/p5.1 tdo/p5.3 tms/p5.2 sda/cs0 scl/so-si irmck171 (top view) ain2 cmext p2.0/nmi p1.0/t2 p3.0/cs1 13 ain3 ain4 vdd1 ain1 ain0 ain5+ ain5- ain5o p3.3/int1 p3.1/aopwm2 figure 2 pinout of irmck171
irmck171 7 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 3 irmck171 block diagram and main functions irmck171 block diagram is shown in figure 3 . motion control sequencer dual port ram 2 kbyte mce program ram 12 kbyte program rom / ram 32 kb 8 bit up address / data bus motion control bus a / d mux s / h d / a ( pwm ) timer counnter 0 , 1 , 2 watchdog timer motion control modules uart i 2 c snd rcv 6 low loss svpwm ain 0 gatekill to igbt gate drive mini - motion control engine ( mini mce ) monitoring host interface digital i / os 8 bit ( 8051 ) microcontroller ain 1 ain 2 jtag emulator debugger 4 freq synthesizer 2 ceramic resonator ( 4 mhz ) 3 2 mhz ain 3 analog input 2 capture interrupt control single shunt motor current reconstruction from shunt resistor speed command port 1 scl sda port 2 port 3 ain 4 8 bit cpu core local ram 2 kbyte 128 mhz ifb 3 ain 5 3 figure 3 irmck171 block diagram irmck171 contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o sensorless foc (complete sensorless field oriented control) o proportional plus integral block o lo w pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch o peak detect
irmck171 8 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 o transition o multiply - divide (signed and unsigned) o divide (signed and unsigned) o adder o sub tractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16 bit wide logic operations (and, or, xor, not, negate) o mce tm program memory and dual port ram (max 12k+2k byte) o mce tm control se quencer ? 8051 microcontroller o two 16 bit timer/counters o one 16 bit periodic timer o one 16 bit watchdog timer o one 16 bit capture timer o up to 24 discrete i/os o six - channel 12 bit a/d ? buffered (current sensing) one channel (0 ? 1.2v input) ? unbuffered seven chann els (0 ? 1.2v input) o jtag port (4 pins) o up to three channels of analog output (8 bit pwm) o uart o i 2 c/spi port o 32k byte otp program rom o 2k byte data ram
irmck171 9 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4 application connection and pin function p 1 . 2 / txd p 1 . 1 / rxd p 1 . 3 / sync / sck xtal 0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ain 0 , ain 1 , ain 2 , ain 3 host microcontroller ( rs 232 c ) digital i / o control system clock 4 mhz crystal analog output xtal 1 p 1 . 4 / cap p 3 . 0 / cs 1 reset p 5 . 1 / t di jtag control ( otp programming & emulation ) t clk p 5 . 2 / tms t do avref ifbc + ifbc - ifbco other analog input ( 0 - 1 . 2 v ) avdd 1 . 8 v avss vdd 1 3 . 3 v vss cmext ain 5 + ain 5 - ain 5 o optional external voltage reference ( 0 . 6 v ) p 2 . 7 / aopwm 1 scl / so - si sda / cs 0 other communication ( i 2 c ) frequency synthesizer rs 232 c i 2 c / spi port 1 port 2 reset pwm 1 jtag interface low loss space vector pwm s / h s / h 8051 cpu dual port memory ( 2 kb ) & mce memory ( 12 kb ) motion control modules motion control sequencer 12 bit a / d & mux system clock local ram ( 2 kbyte ) program ram ( 32 kbyte ) system reset watchdog timer timer s irmc k 171 aref port 3 p 1 . 0 / t 2 p 1 . 5 / vpp p 2 . 0 / nmi p 3 . 2 / int 0 4 3 . 3 v 1 . 8 v voltage regulator vddcap 3 . 3 v p 3 . 3 / int 1 otp programming voltage ( 6 . 5 v ) motor hvic gate drive irs 2336 d avref single shunt current sensing figure 4 irmck171 connection diag ram
irmck171 10 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from irmck171 p1.1/rxd input, receive data to irmck171 discrete i/o interface p1.0/t2 input/output port 1.0, can be configured as timer/counter 2 input p1. 1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output, needs to be pulled up to vdd1 in order t o boot from i 2 c eeprom p1.4/cap input/output port 1.4, can be configured as capture timer input p1.5/vpp input/output port 1.5, or otp programming voltage p2.0/nmi input/output port 2.0, can be configured as non - maskable interrupt input p3.2/int0 input/out put port 3.2, can be configured as int0 input p2.7/aopwm1 input/output port 2.7, can be configured as aopwm1 output p3.0/int2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1 p3.1/aopwm2 input/output port 3.1, can be configur ed as aopwm2 output p3.3/int1 input/output port 3.3, can be configured as int1 input p5.1/tdi input port 5.1, configured as jtag port by default p5.2/tms input port 5.2, configured as jtag port by default analog output interface p2.7/aopwm1 input/output, can be configured as 8 - bit pwm output 1 with programmable carrier frequency p3.1/aopwm2 input/output, can be configured as 8 - bit pwm output 2 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesn?t require external rc time constant i 2 c interface scl/so - si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 i 2 c/spi interface scl/so - si output, i 2 c clock output, or spi data sda/cs0 input/output, i 2 c data line or spi chip select 0 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom p3.0/i nt2/cs1 input/output port 3.0, can be configured as int2 input or spi chip select 1
irmck171 11 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal, internally pulled down by 58k? pwmul output, pwm phase u low side gate signal, internally pulled down by 58k? pwmvh output, pwm phase v high side gate signal, internally pulled down by 58k? pwmvl output, pwm phase v low side gate signal, internally pulled down by 58k? pwmwh output, pwm phase w high side gate signal, internally pulled down by 58k? pwmwl output, pwm phase w low side gate signal, internally pulled down by 58k? fault gatekill input, upon assertion, this negates all six pwm si gnals, active low, internally pulled up by 70k? 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) aref 0.6v buffered output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected . ifb+ input, operational amplifier positive input for shunt resistor current sensing ifb - input, operational amplifier negative input for shunt resistor current sensing ifbo output, operational amplifier output for shunt resistor current sensing ain0 inpu t, analog input channel 0 (0 ? 1.2v), typically configured for dc bus voltage input ain1 input, analog input channel 1 (0 ? 1.2v), needs to be pulled down to avss if unused ain2 input, analog input channel 2 (0 ? 1.2v), needs to be pulled down to avss if u nused ain3 input, analog input channel 3 (0 ? 1.2v), needs to be pulled down to avss if unused ain4 input, analog input channel 4 (0 ? 1.2v), needs to be pulled down to avss if unused ain5+ input, operational amplifier positive input for shunt resistor cur rent sensing ain5 - input, operational amplifier negative input for shunt resistor current sensing ain5o output, operational amplifier output for ain5 output, there is a single sample/hold circuit on the output 4.4 power interface group vdd1 digital power (3. 3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not designed to power any external circuits or devices. only capacitors should be connected to this pin. vss digita l common 4.5 test interface group p5.2/tms jtag test mode input or input/output digital port tdo jtag data output p5.1/tdi jtag data input, or input/output digital port
irmck171 12 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 tck jtag test clock
irmck171 13 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min t yp max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 6.0 v respect to vss v pp otp programming voltage - 0.3v - 7.0v respect to vss t a ambient te mperature - 40 ?c - 85 ?c t s storage temperature - 65 ?c - 150 ?c table 1 absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 system clock frequency and power consumption c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25 ?c. symbol parameter min typ max unit sysclk system clock 32 - 128 mhz p d power consumption 160 1) 200 mw table 2 system clock frequency note 1) the value is based on the condition of mce clock=126mhz, 8051 clock 31.5mhz with a actual motor running by a typical mce application program and 8051 code.
irmck171 14 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v pp otp programming voltage 6.70v 6.75v 6.80v recommende d v il input low voltage - 0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high l evel output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3 digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so - si, sda/cs0 pins. (3) applied to all digital i/o pins except scl/so - si and sda/cs0 pi ns.
irmck171 15 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.4 analog i/o (ifb+,ifb - ,ifbo, ain5+,ain5 - ,ain5o) dc characteristics c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb - op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 4 analog i/o dc characteristics note: (1) data guaranteed by design.
irmck171 16 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.5 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc+ u vcc positive going threshold 2.78 v 3.04 v 3.23 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3.23 v uv cc h uvcc hysteresys - 73 mv - (1) table 5 uvcc dc characteristics note: (1) data guaranteed by design. 5.6 itrip compa rator dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - itrip - itrip negative going threshold - 1.10v - itriph itrip hysteresys - 120mv - table 6 itrip dc characteristics 5.7 cmext and aref cha racteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25?c. symbol parameter min typ max condition v cm cmext voltage 495 mv 600 mv 700 mv vdd1 = 3.3 v (1) v aref buffer output voltage 495 mv 600 mv 700 mv vdd1 = 3.3 v ? v o load regulation (v dc - 0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 7 cmext and aref dc characteristics note: (1) data guaranteed by design.
irmck171 17 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6 ac characteristics 6.1 digital pll ac characteristics symbol parameter min typ m ax condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 8 pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =1 k c 1 =30pf c 2 = 30pf figure 3 crystal circuit example
irmck171 18 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.2 analog to digital converter ac characteristics unless specified, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 9 a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage figure 4 voltage droop and s/h hold time
irmck171 19 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.3 op amp ac characteristics unless specified, ta = 25?c. sym bol parameter min typ max condition op sr op amp slew rate - 10 v/sec - vdd1 = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 - (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 10 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pf, see figure 5 . here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. avref ifbc + ifbc- ifbco irmck171 ic external components 47pf figure 5 a capacitor of 47pf is recommended at the output pin of all op amps.
irmck171 20 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.4 sync to svpwm and a/ d conversion ac t iming sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 6 sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - 5 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 11 sync ac characteristics note: (1) ain1 through ain5 channels are converted once eve ry 6 sync events
irmck171 21 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.5 gatekill to svpwm ac t iming gatekill pwmux , pwmvx , pwmwx t w gk t d gk figure 7 gatekill timing unless specified, ta = 25 ?c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 12 gatekill to svpwm ac timing 6.6 itrip ac timing itrip pwmuh,pwmul, pwmvh,pwmvh, pwmwh,pwmwl t itrip figure 8 itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 13 itrip ac timing
irmck171 22 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.7 interrupt ac timing p3.2/int0 p3.3/int1 internal program counter internal vector fetch t wint t dint figure 9 interrupt timing unless specified, ta = 25?c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 14 interrupt ac timing 6.8 i 2 c ac timing scl sda t i 2 st 1 t i 2 st 2 t i 2 wsetup t i 2 clk t i 2 whold t i 2 rsetup t i 2 rhold t i 2 clk t i 2 en 1 t i 2 en 2 figure 10 i 2 c timing unless specified, ta = 25?c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk tab le 15 i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication.
irmck171 23 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.9 spi ac timing spi write ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t wrdelay t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csdelay figure 11 spi write timing unless specified, ta = 25?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 16 spi write ac timing
irmck171 24 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 spi read ac timing p 1 . 3 / sync / sck scl / s o - s i t spiclk t rdsu t cshold sda / cs 0 p 3 . 0 / int 2 / cs 1 t cshigh bit 7 ( msb ) bit 0 ( lsb ) t spiclkht t spiclklt t csrd t rdhold figure 12 spi read timing unless specified, ta = 25 ?c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 17 spi read ac timing
irmck171 25 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.10 uart ac timing txd rxd data and parity bit start bit t baud stop bit t uartfil figure 13 uart timing unless specified, ta = 25 ?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 18 uart ac timing note: (1) each bit including start and stop bit is sampled three tim es at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
irmck171 26 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.11 capture input ac timing p1.4/cap crev(h,l ) internal register t caphigh t capclk t crdelay t caplow t cldelay clast(h,l) internal register t intdelay interrupt vector fetch interrupt figure 14 capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 syscl k t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 19 capture ac timing
irmck171 27 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.12 otp programming timing tck tdi/tms vpp t vps t vph 6.75v vdd/vss/floating vdd/vss/floating figur e 15 otp programming timing unless specified, ta = 25?c. symbol parameter min typ max unit t vps vpp setup time 10 - - nsec t vph vpp hold time 15 - - nsec table 20 otp programming timing
irmck171 28 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.13 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 16 jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to t do propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 21 jtag ac timing
irmck171 29 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 7 i/o structure the following figure shows the motor pwm output (pwmuh/pwmul/pwmvh/pwmvl/ pwmwh/pwmwl) 270 ? 6.0v 6.0v internal digital circuit high true logic vdd1 (3.3v ) vss 58k ? pin figure 17 pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh output the following figure shows the digital i/o structure except the motor pwm output 6 . 0 v 6 . 0 v internal digital circuit low true logic vdd 1 ( 3 . 3 v ) 70 k ? pin vss 270 ? figure 18 all digital i/o except motor pwm output
irmck171 30 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 the following figure shows reset and gatekill i/o structure. 270 ? 6 . 0 v 6 . 0 v reset gatekill circuit vdd 1 ( 3 . 3 v ) 70 k ? pin vss figure 19 reset, gatekill i/o the following figure shows the analog input structure. 1 ? 6.0v 6.0v analog input pin avss analog circuit vddcap(1.8v) figure 20 analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit vddcap(1.8v) figure 21 analog operational amplifier output and aref i/o structure
irmck171 31 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 the following figure shows the vpp pin structure pin vss 8 . 0 v 270 ? figure 22 vpp programming pin i/o structure the following figure shows the vss and avss pins structure pin vdd1 avdd 6.0v figure 23 vss and avss pin structure the following figure shows the vdd1 and vddcap pin structure pin vss 6 . 0 v figure 24 vdd1 and vddcap pin s tructure the following figure shows the xtal0 and xtal1 pins structure 1 ? 6.0v 6.0v pin vss vddcap(1.8v) figure 25 xtal0/xtal1 pins structure
irmck171 32 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 8 pin list pin number pin name internal pull - up /pull - down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.0/t2 i/o discrete programmable i/o or timer/counter 2 input 4 scl/so - si i/o i 2 c clock output (open drain, need pull up) or spi data 5 sda/cs0 i/o i 2 c data (open drain, need pull up) or spi chip select 0 6 p1.3/sync/sck i/o discrete programmable i/o or sync output or spi clock output, needs to be pulled up to vdd1 in order to boot from i 2 c eeprom 7 p1.4/cap i/o discrete programmable i/o or capture timer input 8 vdd1 p 3.3v digital power 9 vss p d igital common 10 vddcap p internal 1.8v output, capacitor(s) to be connected 11 p2.0/nmi i/o discrete programmable i/o or non - maskable interrupt input 12 p3.2/int0 i/o discrete programmable i/o or interrupt 0 input 13 p2.7/aopwm1 i/o discrete prog rammable i/o or pwm 1 digital output 14 ain0 i analog input channel 0, 0 - 1.2v range, needs to be pulled down to avss if unused 15 ain1 i analog input channel 1, 0 - 1.2v range, needs to be pulled down to avss if unused 16 ain2 i analog input channel 2, 0 - 1.2v range, needs to be pulled down to avss if unused 17 ain3 i analog input channel 3, 0 - 1.2v range, needs to be pulled down to avss if unused 18 ain4 i analog input channel 4, 0 - 1.2v range, needs to be pulled down to avss if unused 19 ifb - i sin gle shunt current sensing op amp input ( - ) 20 ifb+ i single shunt current sensing op amp input (+) 21 ifbo o single shunt current sensing op amp output 22 cmext o unbuffered 0.6v output. capacitor needs to be connected. 23 aref o analog reference v oltage output (0.6v) 24 ain5 - i analog input channel 5, 0 - 1.2v range, needs to be pulled down to avss if unused 25 ain5+ i analog input channel 5, 0 - 1.2v range, needs to be pulled down to avss if unused 26 ain5o o analog output 5, 0 - 1.2v range, 27 avss p analog common 28 vddcap p internal 1.8v output, capacitor(s) to be connected 29 vdd1 p 3.3v digital power 30 vss p digital common 31 p3.1/aopwm2 i/o discrete programmable i/o or pwm 2 digital output
irmck171 33 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 pin number pin name internal pull - up /pull - down pin type description 32 pwmwl 58 k pull down o pwm gate d rive for phase w low side, configurable either high or low true. 33 pwmvl 58 k pull down o pwm gate drive for phase v low side, configurable either high or low true 34 pwmul 58 k pull down o pwm gate drive for phase u low side, configurable either hig h or low true 35 pwmwh 58 k pull down o pwm gate drive for phase w high side, configurable either high or low true 36 pwmvh 58 k pull down o pwm gate drive for phase v high side, configurable either high or low true 37 pwmuh 58 k pull down o pwm gate drive for phase u high side, configurable either high or low true 38 p1.5/vpp i/o p otp programming power (6.5v) or discrete programmable i/o. 39 gatekill 70 k pull up i pwm shutdown input, 2 - sec digital filter, configurable either high or low true. 40 p3.0/int2/cs1 70 k pull up i/o discrete programmable i/o or external interrupt 2 input or spi chip select 1 41 p5.2/tms i/o jtag test mode select or discrete i/o 42 tdo o jtag test data output 43 p5.1/tdi i/o jtag test data input or discrete i /o 44 tck i jtag test clock 45 reset i/o reset, low true, schmitt trigger input 46 p1.1/rxd i/o uart receiver input or discrete programmable i/o 47 p1.1/rxd i/o uart transmitter output or discrete programmable i/o 48 p3.3/int1 i/o interrupt 1 inp ut or discrete i/o table 22 pin list
irmck171 34 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 9 package dimensions
irmck171 35 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 10 part marking information irmck 171 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier 11 qualification information qualification level industrial ?? (per jedec jesd 4 7e) moisture sensitivity level msl3 ??? (per ipc/jedec j - std - 020c) esd machine model class b (per jedec standard jesd22 - a114d) human body model class 2 (per eia/jedec standard eia/jesd22 - a115 - a) rohs compliant yes ? qualification standards can be foun d at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information.
irmck171 36 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 data and spe cifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 -7105 tac fax: (310) 252 -7903 visit us at www.irf.com for sales contact information

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